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| HI-8590 January 2001 ARINC 429 LINE DRIVER AND LINE RECEIVER PIN CONFIGURATION DESCRIPTION The HI-8590 is a CMOS integrated circuit with independent ARINC 429 line driver and line receiver in a single 16 pin package. Both ARINC 429 functions are implemented in analog/digital CMOS. The line driver function in the HI-8590 connects directly to the ARINC bus and translates CMOS/TTL input levels to ARINC 429 specified amplitudes using built-in zeners. The slope of the differential output signal is controlled by a single logic input without the use of any external capacitors. A internal 37.5 ohm resistor is provided in series with each line driver output. The line driver function is the same as Holt's 8 pin stand-alone HI-8585 line driver. The line receiver interfaces directly to the ARINC 429 bus and translates incoming ARINC levels to levels compatible with CMOS logic. Internal comparator levels are set just below the standard 6.5 volt minimum data threshold and just above the standard 2.5 volt maximum null threshold The TESTA and TESTB inputs of the line receiver allow bypassing the analog input circuitry for testing purposes. Also, if both test inputs are taken high, the receiver's digital outputs are tri-stated allowing wire-or possibilities. The line driver function is the same as Holt's 8 pin stand-alone HI-8588 line receiver. V+ 1 TESTB 2 16 VCC 15 SLP1.5 14 TESTA 13 RINB 12 RINA 11 TX0IN 10 TX1IN 9 GND ROUTB 3 ROUTA 4 TXBOUT 5 TXAOUT 6 N/C 7 V- 8 SUPPLY VOLTAGES Vcc = +5V 5% V+ = 12V to 15V V- = -12V to -15V PIN DESCRIPTION TABLE PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 FEATURES SYMBOL V+ TESTB ROUTB ROUTA TXBOUT TXAOUT N/C VGND TX1IN TX0IN RINA RINB TESTA SLP1.5 VCC FUNCTION POWER LOGIC INPUT LOGIC OUTPUT LOGIC OUTPUT ARINC OUTPUT ARINC OUTPUT NO CONNECT POWER POWER LOGIC INPUT LOGIC INPUT ARINC INPUT ARINC INPUT LOGIC INPUT LOGIC INPUT POWER DESCRIPTION +12 TO + 15 VOLTS CMOS RECEIVER CMOS OUTPUT B RECEIVER CMOS OUTPUT A LINE DRIVER TERMINAL B LINE DRIVER TERMINAL A ! ! ! ! ! ! Direct ARINC 429 interface to line driver and line receiver Both functions in a single 16 pin package Line Driver ! Internal zener sets output levels ! Digital output slope control ! CMOS/TTL logic pins Line Receiver -12 TO -15 VOLTS GROUND CMOS OR TTL CMOS OR TTL RECEIVER A INPUT RECEIVER B INPUT CMOS CMOS OR TTL, V+ IS OK +5 VOLT SUPPLY ! Input hystersis at least 2 volts ! Test inputs bypass analog inputs ! Output tri-state mode Plastic thermally enhanced surface mount (ESOIC) package Mil-temperature range available (DS8590 Rev. B) HOLT INTEGRATED CIRCUITS 1 01/01 HI-8590 FUNCTION TABLES LINE DRIVER TX1IN 0 0 0 1 1 1 TX0IN 0 1 1 0 0 1 SLP1.5 X 0 1 0 1 X TXAOUT 0V -5V -5V 5V 5V 0V TXBOUT 0V 5V 5V -5V -5V 0V SLOPE N /A 10s 1.5s 10s 1.5s N /A RINA LINE RECEIVER RINB TESTA TESTB ROUTA ROUTB 0 0 0 0 1 1 0 0 0 1 0 1 0 0 1 0 1 HI-Z 0 1 0 1 0 HI-Z -1.25V to 1.25V -1.25V to 1.25V -3.25V to -6.5V 3.25V to 6.5V X X X 3.25V to 6.5V -3.25V to -6.5V X X X FUNCTIONAL DESCRIPTION LINE DRIVER Figure 1 is a block diagram of the line driver. The +5V and -5V levels are generated internally using on-chip zeners. Currents for slope control are set by zener voltages across on-chip resistors. The TX0IN and TX1IN inputs receive logic signals from a control transmitter chip such as the HI-6010 or HI-8282. TXAOUT and TXBOUT hold each side of the ARINC bus at Ground until one of the inputs becomes a One. If for example TX1IN goes high, a charging path is enabled to 5V on an "A" side internal capacitor while the "B" side is enabled to -5V. The charging current is selected by the SLP1.5 pin. If SLP1.5 is high, the capacitor is nominally charged from 10% to 90% in 1.5s. If low, the rise and fall times are 10s. A unity gain buffer receives the internally generated slopes and differentially drives the ARINC line. Current is limited by the series output resistors at each pin. There are no fuses in series with the ARINC outputs of the HI-8590 as exists on the HI-8382. The HI-8590 has 37.5 ohms in series with each ARINC output just like the HI-8585. The HI-8586 has 10 ohms in series. The HI-8586 is used with the HI-8588 for applications where more series resistance is added externally, typically for lightning protection devices. The line driver inputs TX1IN, TX0IN, & SLP1.5 must be tied to either a logic high or low if not used. 5V ONE "A" SIDE CURRENT CONTROL TXAOUT 37.5 OHMS NULL ZERO -5V ESD PROTECTION AND VOLTAGE TRANSLATION CONTROL LOGIC SLP1.5 5V ONE "B" SIDE CURRENT CONTROL TXBOUT NULL ZERO CONTROL LOGIC 37.5 OHMS -5V FIGURE 1 - LINE DRIVER BLOCK DIAGRAM HOLT INTEGRATED CIRCUITS 2 HI-8590 FUNCTIONAL DESCRIPTION (cont.) RECEIVER Figure 2 shows the general architecture of the ARINC 429 receiver. The receiver operates off the VCC supply only. The inputs RINA and RINB each have series resistors, typically 35K ohms. They connect to level translators whose resistance to Ground is typically 10K ohms. Therefore, any series resistance added to the inputs will affect the voltage translation. After level translation, the inputs are buffered and become inputs to a differential amplifier. The amplitude of the differential signal is compared to levels derived from a divider between VCC and Ground. The nominal settings correspond to a One/Zero amplitude of 6.0V and a Null amplitude of 3.3V. The status of the ARINC receiver input is latched. A Null input resets the latches and a One or Zero input sets the latches. The logic at the output is controlled by the test signal which is generated by the logical OR of the TESTA and TESTB pins. The receiver output pins float if both TESTA and TESTB are a logic One. ONE S Q LATCH R TEST ROUTA TEST TESTA TESTA ' TESTB RINA RINB ESD PROTECTION AND TRANSLATION NULL TEST ZERO S Q LATCH R ROUTB TEST TESTA ' TESTB TESTB NULL FIGURE 2 - RECEIVER BLOCK DIAGRAM APPLICATION INFORMATION 16 1 4 3 Figure 3 shows a possible application of the HI-8590 interfacing both the ARINC transmit and receive channels of a HI-6010 which in turn interfaces to an 8-bit microprocessor bus. HARDWIRE OR DRIVE FROM LOGIC i i i 14 2 15 HI-8590 12 13 HI-6010 6 5 11 10 9 8 FIGURE 3 - APPLICATION DIAGRAM HOLT INTEGRATED CIRCUITS 3 HI-8590 ABSOLUTE MAXIMUM RATINGS All voltages referenced to GND Supply voltages VCC ................................................. +7.0V V+..................................................... +20V V- ...................................................... -20V Voltage on inputs ARINC pin .......................... +29V to - 29V TX1IN, TX0IN or SLP1.5 ...-0.3 to V+ +0.3 All other input pins............-0.3 to VCC +0.3 DC current per input pin ................. +10mA Power dissipation at 25C Plastic SO ........................................ 1.0W Thermal Resistance - ja .............. 98C/W Solder Temperature Leads ....................... +280C for 10 sec Package body ............................+220C Storage Temperature ....... -65C to +150C Supply Voltages Vcc ................................................+5V 5% V+........................+12V 5% or +15V 10% V-..........................-12V 5% or -15V 10% Temperature Range Industrial Screening ............ -40C to +85C Hi-Temp Screening ........... -55C to +125C Junction Temperature, Tj ................. +175C RECOMMENDED OPERATING CONDITIONS NOTE: Stresses above absolute maximum ratings or outside recommended operating conditions may cause permanent damage to the device. These are stress ratings only. Operation at the limits is not recommended. DC ELECTRICAL CHARACTERISTICS Vcc = 5V 5%, V+ = 12V to 15V, V- = -12V to -15V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS Line Driver Input voltage (TX1IN, TX0IN, SLP1.5) high low Input current (TX1IN, TX0IN, SLP1.5) source sink ARINC output voltage (TXAOUT, TXBOUT) one or zero null ARINC output impedance (TXAOUT, TXBOUT) SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VIH VIL 2.1 - - V+ 0.5 volts volts A A volts volts ohm IIH IIL VDOUT VNOUT ZOUT VIN = 0V VIN = 5V - 5.00 37.5 0.1 0.1 5.50 0.25 - magnitude at pin & no load 4.50 " "" "" -0.25 Note1 - Notes : 1. The output resistance is checked by measuring the momentary short circuit current at each ARINC output pin. HOLT INTEGRATED CIRCUITS 4 HI-8590 DC ELECTRICAL CHARACTERISTICS (cont.) Vcc = 5V 5%, V+ = 12V to 15V, V- = -12V to -15V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS Line Receiver ARINC input voltage (RINA, RINB) one or zero null common mode Logic input voltage (TESTA, TESTB) high low ARINC input resistance RINA to RINB RINA or RINB to GND or VCC Logic input current (TESTA, TESTB) source sink Logic output current (ROUTA, ROUTB) one zero Operating Supply Current VCC - operating (TESTA & TESTB = 0V) V+ V- SYMBOL TEST CONDITIONS MIN TYP MAX UNITS VDIN VNIN VCOM differential voltage " " with respect to GND 6.5 - 10.0 - 13.0 2.5 5.0 volts volts volts VIH VIL RDIFF RSUP supplies floating " " 3.5 30 19 75 40 1.5 - volts volts Kohm Kohm A A mA mA IIH IIL VIN = 0V VIN = 5V - - 0.1 0.1 IOH IOL VOH = 4.6V VOL = 0.4V 3.6 -1.6 5.6 -0.8 - ICC IDD IEE RINA, RINB open V+ = +15V no load SLP1.5 = V+ TX1IN, TX0IN = 0V -12.0 5.3 6.0 -6.0 8.5 12.0 - mA mA mA AC ELECTRICAL CHARACTERISTICS Vcc = 5V 5%, V+ = 12V to 15V, V- = -12V to -15V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS Line Driver Propagation delay Output high to low Output low to high Transition times Output high to low & low to high Output high to low & low to high Line driver input capacitance Logic SYMBOL TEST CONDITIONS MIN TYP MAX UNITS defined in Figure 4, no load t phlx t plhx 500 500 ns ns t fx & t rx t fx & t rx SLP1.5 = logic 1 SLP1.5 = logic 0 1.0 5 1.5 10 2.0 15 s s CIN Guaranteed but not tested - - 10 pF HOLT INTEGRATED CIRCUITS 5 HI-8590 AC ELECTRICAL CHARACTERISTICS (cont.) Vcc = 5V 5%, V+ = 12V to 15V, V- = -12V to -15V, GND = 0V, TA = Operating Temperature Range (unless otherwise specified). PARAMETERS Line Receiver Propagation delay Output high to low Output low to high Transition times Output high to low Output low to high Line receiver input capacitance (1) ARINC differential ARINC single ended to GND Logic SYMBOL TEST CONDITIONS MIN TYP MAX UNITS defined in Figure 5, CL = 50pF t phlr t plhr 600 600 ns ns t fr t rr - 50 50 80 80 ns ns CAD CAS CIN - 5 - 10 10 10 pF pF pF Notes: 1. Guaranteed but not tested HI-8590 PACKAGE THERMAL CHARACTERISTICS M AXIMUM ARINC LOAD PACKAGE STYLE 1 ARINC 429 DATA RATE 5 SUPPLY CURRENT (mA) 2 Ta = 25 oC Ta = 85 oC Ta=125 oC JUNCTION TEMP, Tj (C) Ta = 25 oC Ta = 85 oC Ta=125 oC 16 Le a d Plastic SOIC Low Speed High Speed 3 4 16.7 27.1 16.8 26.3 16.9 26.1 52 68 112 121 150 162 TXAO U T and TXBOUT Shorted to Ground 6, 7 PACKAGE STYLE 1 ARINC 429 DATA RATE 5 SUPPLY CURRENT (mA) 2 Ta = 25 C o JUNCTION TEMP, Tj (C) Ta = 25 oC Ta = 85 oC Ta=125 oC Ta = 85 C o Ta=125 C o 16 Le a d Plastic SOIC Low Speed High Speed 3 4 51.3 46.0 46.4 39.7 45.7 39.5 117 122 168 171 194 206 Notes: 1. All data taken on devices soldered to single layer copper PCB (3" X 4.5" X .062"). 2. At 100% duty cycle, 15V power supplies. For 12V power supplies multiply all tabulated values by 0.8. 3. Low Speed: Data Rate = 12.5 Kbps, Load: R = 400 Ohms, C = 30 nF. 4. High Speed: Data Rate = 100 Kbps, Load: R = 400 Ohms, C = 10 nF. Data not presented for C = 30 nF as this is considered unrealistic for high speed operation. 5. 16 Lead Plastic SOIC (Thermally enhanced with built-in heat sink). 6. Similar results would be obtained with TXAOUT shorted to TXBOUT. 7. For applications requiring survival with continuous short circuit, operation above Tj = 175C is not recommended. HOLT INTEGRATED CIRCUITS 6 HI-8590 TX1IN t phlx t plhx TX0IN t phlx t rx t rx 90% 5V 0V t plhx 5V 0V VDIFF TXAOUT - TXBOUT 10% 90% 10% 10% 10V 0V -10V t fx t fx FIGURE 4 - LINE DRIVER TIMING VDIFF RINA -RINB t plhr t phlr ROUTA 90% 10% 10V 0V -10V t rr 5V 0V t fr 5V 0V FIGURE 5 - RECEIVER TIMING t plhr ROUTB t phlr ORDERING INFORMATION PART PACKAGE TEMPERATURE BURN LEAD NUMBER HI-8590PSI HI-8590PST DESCRIPTION 16 PIN PLASTIC ESOIC - WB 16 PIN PLASTIC ESOIC - WB RANGE -40C TO +85C -55C TO +125C FLOW I T IN NO NO FINISH SOLDER SOLDER Legend: ESOIC - Thermally Enhanced Small Outline Package (SOIC w/built-in heat sink) WB - Wide Body HOLT INTEGRATED CIRCUITS 7 HI-8590 PACKAGE DIMENSIONS inches (millimeters) 16-PIN PLASTIC SMALL OUTLINE (ESOIC) - WB (Wide Body, Thermally Enhanced) - HI-8590 Only .406 .004 (10.30 .10) Heat sink stud on top of package Package Type: 16HWE2 .0098 (.25) .406 .008 (10.30 .20) Top View .140 .002 (3.55 .05) .295 .004 (7.50 .10) R .040 Typ (R 1.02 Typ) .245 .002 (6.23 .05) Detail A .093 .002 (2.35 .05) 7 Typ 0 to 7 .050 (1.270) .018 .002 (.457 .05) .035 .004 (.90 .10) .0079 .0039 (.20 .10) Detail A HOLT INTEGRATED CIRCUITS 8 |
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